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Support #315

How to define an expression containing strings

Added by Kai Liu about 2 years ago. Updated 4 months ago.

Status:
Closed
Priority:
Low
Target version:
Start date:
Due date:
% Done:

100%


Description

In the component editor, I defined a parameter called a string variable user_var, which has a default value "fpga".
Depending on the value of this variable, I want to make several registers invisible, so I defined an expression in the "Is present, f(x)" field of a register like the following:
user_var=="fpga"
This is a valid SystemVerilog expression and can be evaluated to 0 or 1, but the validation failed with this expression. My question is: how to define an expression containing strings?
Thanks.
/Kai

History

#1 Updated by Esko Pekkarinen about 2 years ago

  • Priority changed from Normal to Low
  • Target version set to Longterm

String comparison is not supported yet.

#2 Updated by Esko Pekkarinen 5 months ago

  • Target version changed from Longterm to 3.6

#3 Updated by Esko Pekkarinen 4 months ago

  • Status changed from New to Closed
  • Assignee set to Esko Pekkarinen
  • % Done changed from 0 to 100

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