How to define an expression containing strings
In the component editor, I defined a parameter called a string variable user_var, which has a default value "fpga".
Depending on the value of this variable, I want to make several registers invisible, so I defined an expression in the "Is present, f(x)" field of a register like the following:
This is a valid SystemVerilog expression and can be evaluated to 0 or 1, but the validation failed with this expression. My question is: how to define an expression containing strings?