Bug #331
Verilog inout slicing not supported
0%
Description
Generated verilog inout connections have to be directly connected to a wire or a port of the encompassing component, since assignments are one directional.
Steps to reproduce:- Create a design with interconnections connecting inout ports
- Make sure that there are slicing for inout ports: Either through port mapping or ad-hoc part selection.
- Generate Verilog from the design
Expected result:
The generated Verilog somehow supports slicing, so that the same port may be have multiple connections.
Actual result:
Only one connection is in each inout port.
Environment (OS, K2 version etc.):
Kactus2 3.3.384 32-bit, Verilog generator 2.0
Additional information:
As far is currently known, the potential fix would be either: 1. Generating some sort of intermediate module for slicing. 2. Replace current assignment based slicing with connection lists.
Associated revisions
[CORRECTIVE] Fixed more glitches on generating one bit connections. Moreover, now the hierarchical inout connections pick slicing from top port. (refs #331).
[CLEANUP] Cleaned the code used to write Verilog for inout connections. (refs #331).
History
#1 Updated by Janne Virtanen about 7 years ago
It appears that the ports of the encompassing component cannot be sliced with concatenated lists of wires. The instance ports could be sliced so, but it is not supported unless there is enough demand for it.
#2 Updated by Esko Pekkarinen about 7 years ago
- File IOcases.svg View added