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Bug #343

Multiple port mapping not correct

Added by Richard Schindler about 1 year ago.

Status:
New
Priority:
Normal
Assignee:
-
Target version:
-
Start date:
Due date:
% Done:

0%


Description

Mapping a physical port to multiple interfaces is not implemented correctly within Verilog generator.
In the attached example Sink_0_clk signal is not driven.

I used K2 Windows Version 3.4.3 32-bit.

MultipleMapping.zip (5.61 KB) Richard Schindler, 27.03.2017 12:02 PM

Also available in: Atom PDF