Feature #369
Feature #368: Hierarchical verilog import
Import verilog sub-instances
Start date:
04.02.2019
Due date:
15.02.2019
% Done:
30%
Description
Add feature to import sub-instances in a verilog file.
Considerations:
What VLNVs are assigned to new components? How to map to existing components?
a) Provide template?
b) Have a table of found modules, their files and VLNVs
How to locate implementation files?
- Must import all ports and parameters
Should we recurse through sub-modules?
- Later
Details
After reading through the file, create a table of found modules. User will fill in the VLNV and path to the implementation file. Then import the implementation file as before. Create a design and instantiate the found sub-modules.
Associated revisions
[ADDITIVE] Added verilog sub-instances to the import editor (refs #369).
History
#1 Updated by Esko Pekkarinen about 5 years ago
- Due date changed from 01.02.2019 to 15.02.2019
- Start date changed from 28.01.2019 to 04.02.2019
#2 Updated by Mikko Teuho almost 5 years ago
- % Done changed from 0 to 30