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Feature #41

Default name for connections in design view

Added by Anonymous over 10 years ago. Updated over 10 years ago.

Status:
New
Priority:
Low
Assignee:
-
Target version:
Start date:
01.08.2013
Due date:
% Done:

0%

Milestones:

Description

The default names could be constructed as but now they are , where i is the initial point in drawing and f is the final.
This would make the generated VHDL clearer even if user does not edit the names.

The desired naming style is "master_slave_name" instead of "i_f_name".

History

#1 Updated by Anonymous over 10 years ago

  • Tracker changed from Bug to Feature

#2 Updated by Anonymous over 10 years ago

  • Priority changed from Normal to Low

#3 Updated by Esko Pekkarinen over 10 years ago

  • Target version set to Longterm

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