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Feature #49

VHDL generator: signal inclusion and naming, default source

Added by Anonymous over 10 years ago. Updated over 10 years ago.

Status:
New
Priority:
Normal
Assignee:
-
Target version:
Start date:
01.08.2013
Due date:
% Done:

0%

Milestones:

Description

  1. Occasionally, VHDL generator does not include all the ports to the component declaration and ModelSim does not allow simulation since they are in the entity.
  2. Signal names should put undercore between target and logical signal name, e.g. tester_to_hibi_DATA instead of tester_to_hibiDATA. Very simple to do.
  3. The default values for signal map can come from two sources: abstraction definition and port definition. The former overrides the latter which is bit confusing although it's in accordance with IP-XACT standard. It would be easy to print a comments, like "we_in <= '0' -- port default" and "re_in <= '0' -- absdef default". Please use absdef instead of abstraction definition.
  4. The default values in absdef are integers and they must converted to std_logic and std_logic_vector.

History

#1 Updated by Esko Pekkarinen over 10 years ago

  • Target version set to Longterm

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