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# Project Tracker Status Priority Subject Assignee Updated Target version Parent task Estimated time
343Kactus2BugNewNormalMultiple port mapping not correct27.03.2017 12:12 PM
342Kactus2BugIn ProgressNormalMissing default value for unused bitsJanne Virtanen23.03.2017 03:13 PM30.00
273Kactus2BugNewNormalParameters are not written to generated HDL03.09.2015 10:04 PM
257Kactus2BugNewNormalCopy-paste of rows occaisionally loses data17.07.2015 01:20 AM
141Kactus2FeatureNewNormalmemory map design features05.09.2014 02:29 PM
97Kactus2FeatureNewNormalNickname for VLNVs18.12.2013 12:21 PMKactus2 - 2.10
57Kactus2FeatureNewHighCategorization for HW components 18.12.2013 08:49 AMKactus2 - 2.10
24Kactus2FeatureNewNormalComments for IP-XACT elements21.10.2013 08:20 AMKactus2 - 2.10
23Kactus2FeatureNewNormalLicense management27.09.2013 01:18 PMKactus2 - 2.10
19Kactus2FeatureNewNormalLicense and write protection to libraries27.09.2013 01:17 PMKactus2 - 2.10
5Kactus2FeatureNewNormalSVN integration27.09.2013 01:18 PMKactus2 - 2.10
3Kactus2FeatureNewNormalAltera application makefile generator18.12.2013 08:40 AMKactus2 - 2.10
94Kactus2FeatureIn ProgressHighNotesEsko Pekkarinen27.05.2014 12:26 PMKactus2 - 2.930.00
81Kactus2FeatureNewNormalConnectivity visualization18.12.2013 08:40 AMKactus2 - 2.9
60Kactus2FeatureNewNormalConnectivity analysis between components 27.09.2013 01:29 PMKactus2 - 2.9
18Kactus2FeatureNewNormalMemory base/remap addresses to visibility control in HW design27.09.2013 01:28 PMKactus2 - 2.9
363Kactus2BugNewNormalXML comments not handled property21.09.2018 09:21 AMKactus2 - 3.7
362Kactus2FeatureNewNormalComponent transactional ports08.06.2018 11:30 AMKactus2 - 3.7Feature #304
360Kactus2FeatureNewNormalAdd support for isInformative attribute in PortMapsEsko Pekkarinen07.05.2018 10:09 AMKactus2 - 3.7
346Kactus2FeatureNewNormalExpand port importing from abstraction definitionsEsko Pekkarinen13.06.2018 11:43 AMKactus2 - 3.710.00
304Kactus2FeatureNewNormaltransactional port supportMikko Teuho25.06.2018 10:32 AMKactus2 - 3.7
258Kactus2FeatureNewNormalExtending BusDefinition and AbstractionDefinitionMikko Teuho29.06.2018 10:07 AMKactus2 - 3.7
245Kactus2FeatureNewNormalCreate physical ports for a bus interfaceEsko Pekkarinen13.06.2018 11:45 AMKactus2 - 3.724.00
54Kactus2FeatureNewLowUnlocking bus def editing does not show details 13.06.2018 11:48 AMKactus2 - 3.7
331Kactus2BugNewNormalVerilog inout slicing not supported27.02.2017 07:39 AMKactus2 - Longterm
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