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Kactus2: Version 3.5.0 released

Added by Esko Pekkarinen 20 days ago

+ Graphical user interface visual update:
  • All icons updated
  • Instruction labels added in dialogs
  • Colors centralized in KactusColors.h
+ Added feature to show the directory icons provided by OS for library paths which shows version controlled items in Windows
+ Added feature to automatically update library view when file changes on disk
+ Added feature to select the which HW design to open for an IP-XACT component with multiple designs
+ Added editor for indirect interfaces in component + Added editor for component instantiation parameters
+ Added editor for design configuration instantiation parameters
+ Added editor for design configuration instantiation configurable elements
+ Added editor for design instantiation configurable elements
+ Added feature to define prefix in port map auto-connect for better matching
+ Added editor for design parameters
+ Improved performance on drawing connections in design
+ Added delete in context menu in design view
+ Improvements in Memory Designer:
  • Added support for multiple items accessing the same memory map
  • Improved layout for items + Improvements in HTML generation:
  • Added writing register and field reset values in HTML
  • Added writing instantiations within a component in HTML

- Fixed error in XML schema location writing
- Fixed C source editor refresh
- Fixed port size parsign in PADS part generator which previously caused the plugin to crash
- TLMW generator plugin removed from build

  • Software component instance merged to component instance
  • Changed VHDL import to create component parameters and retains references in port boundaries
  • Moved VHDL generator from core to a separate plugin
  • ModelSim generator plugin moved to same framework as Verilog generator

Kactus2: Version 3.4.0 released

Added by Esko Pekkarinen 9 months ago

+ Enhanced features for Memory Designer:
  • Added feature to visualize overlapping memory items
  • Added feature to open the containing component and the editor for the selected item
  • Added feature to visualize local memory maps
  • Changed the visual look of a connection through a bridge
  • Changed display name to be shown instead of element name, if defined
+ Improvements to Verilog generation:
  • Added preview for generated files
  • Added message console for reporting generation status
  • Improved port assignment and vector boundary generation logic

+ Fixed error in importing Verilog ports
+ Added editor for Catalogs
+ Component editor layout updated for most editors
+ Enabled expressions in parameter value when using a choice
+ Added isPresent-property to memory maps, address blocks, address spaces and segments
+ Improved completion help for fileset filetypes and groups
+ Enabled CSV import/export of files in a fileset
+ Added feature to hide immediate values from configurable element values
+ Enabled keyboard navigation in VLNV tree view
+ Added expand/collapse options in VLNV tree view context menu
+ Help and tooltips updated
+ Custom XML namespaces are retained in XML files

- Removed address space reference and base address from mirrored-master bus interface
- Fixed crashing when adding port maps in component
- Fixed a referencing issue with configurable element values when changing active view
- Fixed crashing when a design did not have a configuration
- Fixed crashing when closing a design in specific cases
- Fixed modifications to design connections while the document was unlocked
- Fixed CSV import/export of signal definitions in abstraction definition
- Fixed missing component editor visibility options

  • System mode bus interface coloring changed from red to purple to avoid confusion with invalid interfaces
  • Changed "frozen column" in editors to use vertical headers instead of a separate table
  • Toolbar "Check intergrity" changed to show listing of all errors within the library
    in separate window.
  • Exit screen is displayed longer

Kactus2: Version 3.3.0 released

Added by Esko Pekkarinen about 1 year ago

+ Enhanced features for Memory Designer:
  • Register fields added
  • Compression of items to minimize the required space
    *Multiple address spaces can now be shown as part of the same connection
  • Filtering options added
+ Memory connectivity analysis now manages also instances with identical names
+ File paths within filesets now accept URI expressions
+ Files can be drag-dropped to filesets from the file system
+ Memory map visualization items have now bigger area for expand/collapse
+ Port direction is now checked when a default value is set
+ Port map invert and tieoff are now also shown on the top level of tree hierarchy
+ Zooming now follows mouse location in design
+ Enhanced usage of drafts in design:
  • Bus interface definitions copying when connecting hierarchical draft interface fixed
  • Bus interface definitions copying when connecting non-hierarchical draft interface removed
  • Bus interface definitions and port copying to draft instances changed to take place on packaging of the containing draft component instance
  • Copy-paste of bus interface to a draft component instance changed to copy only the name and the mode of the interface
+ Notification on trying to read XML files of previous standard versions added
+ Improvements to Verilog generation:
  • Generation setup dialog simplified
  • Register definition creation set as optional
  • Module name is correctly used for component instances
  • Environmental identifier created by the generator changed
+ Improvements to Verilog import:
  • Port type parsing improved for Verilog-2001 style ports
  • Parameter parsing improved for lists of parameters
  • Environmental identifier created by the import changed
+ Improved features for MakefileGenerator:
  • Conflicting file selection added
  • Launcher script creation set to optional

- Bus interface creation wizard fixed from preventing user to proceed from the general settings page due to missing port maps
- Component instance replace in design changed to better preserve existing connections
- Port bounds for ad-hoc connections in design fixed
- Author information read from XML fixed
- Symbolic file link usage for XML files fixed
- Toolbar placement at the bottom of main window fixed
- Software views are replaced by views and component instantiations

  • Community guidelines included in manual
  • Settings file path is now shown on the General page of Settings
  • Automatic port mapping changed to less aggressively connect ports
  • Component instance architecture changed to be correctly set by VHDL generator

Kactus2: Version 3.2.0 released

Added by Esko Pekkarinen about 1 year ago

+ Added preliminary version of memory designer:
  • Address spaces and Memory maps within design hierarchy are visualized with their addressing information
  • Connectivity between spaces and maps are visualized
+ Added preliminary version of memory connectivity analysis within designs
  • Added plugin for generating memory listing in CSV format

+ Improvements to Verilog generation
+ Added "Getting started" section to help
+ Fixed performance issues

- Fixed crashing when opening a bus interface without abstraction definition

  • ModelSim Generator moved from core to a separate plugin
KNOWN UNRESOLVED ISSUES:
  • UI issue: paste command does not update usage count of referenced parameters.

Kactus2: Version 3.1.0 released

Added by Esko Pekkarinen over 1 year ago

+ New design for port map editor: * Added feature to auto-connect logical and physical ports * Logical and physical bounds are now easily editable
+ Added support for tieoff values in design and port maps
+ Added feature to copy memory-elements along with their sub-elements
+ Improved expression support: * Basic comparison operators are now accepted * Values true/false are now accepted
+ System group names are now visible and editable in Bus editor
+ Generated Verilog parameters are now correctly ordered for references
+ Performance improvements

  • ModelSim Generator moved from core to a separate plugin
  • XML processing instructions are now retained in IP-XACT files
  • Added option for Linux installation without admin privilidges
KNOWN UNRESOLVED ISSUES:
  • UI issue: paste command does not update usage count of referenced parameters.

Kactus2: Version 3.0.0 released

Added by Esko Pekkarinen over 1 year ago

+ Updated all IP-XACT elements to 2014 standard
+ Improved validation for many IP-XACT elements
+ Updated Verilog generation for one-to-many ad-hoc connections.
+ Added new view related editors for component editor: * Component instantiations * Design instantiations * Design configuration instantiations.
+ Updated port editor to accept ports without defined left and right bounds as ports with a width of 1.
+ Updated parameter referencing.
+ Updated expression parser.
+ Updated component editor memory map visualization.
+ In component editor, changed cut command to copy and remove selected cells of a table.
+ Updated HW design editor: * Updated component instance creation. * Updated component instance removing. * Updated component instance replacing. * Updated connection removing. * Invalid ad-hoc interfaces and ports are displayed with a red colour. * Enabled deleting of invalid ad-hoc interfaces and ports.
+ Usability fixing.

KNOWN UNRESOLVED ISSUES:
  • UI issue: paste command does not update usage count of referenced parameters.

Kactus2: Version 2.8.0 released

Added by Esko Pekkarinen over 2 years ago

+ Added feature to import parameters from include files.
+ Improved configurable element variables editor
  • Synchronizes with the enhanced model parameter definition.
  • The parameters of the top component can be used in the configurable element variables.
  • Variables are now grouped according to their location in the component.

+ Added editors for IP-XACT elements remapState and memoryRemap.
+ Added support for expressions in memory map elements.
+ Added support for parameter references in generated header files.
+ Added feature to save new versions of design configurations and designs.
+ Added support for module parameters to hierarchical views.

KNOWN UNRESOLVED ISSUES:
  • Memory map header generation from a system design does not work properly.
  • Parameters created with version 2.7.0 may not work with the latest release due to change in id formatting. The fastest way to fix this is to re-create the parameters.
  • SystemVerilog expressions are not supported by some features including generators. If expressions or references have been used, it may cause at least the following issues:
    • VHDL generator will generate wrong values.
    • Port maps will not automatically adjust to changes in port size.
  • VHDL import does not preserve references to model parameters.
  • In ports editor, creating a bus interface through ports is not possible for name column.

Kactus2: Version 2.7.0 released

Added by Esko Pekkarinen almost 3 years ago

New features:
+ Added support for SystemVerilog expressions in * component parameter and model parameter value, * component port bounds and default value, * component register offset, size and dimension and * design configurable element values.
+ Added support for referencing parameter and model parameter values in expressions.
+ Added autocomplete feature for available parameter names in expressions.
+ Added feature to view all elements referencing a parameter or model parameter.
+ Configurable element values editor now automatically shows the configurable elements in component instance, their current and default value.
+ Added feature to show/hide elements of a component in component editor.
+ Added support for component choices.
+ Enabled different signal widths for master and slave modes in abstraction definition.
+ Improved ribbon toolbar.

KNOWN UNRESOLVED ISSUES:
SystemVerilog expressions are not supported by some features including generators. If expressions or references have been used, it may cause at least the following issues:
  • Memory map header generator will generate wrong offsets for registers.
  • Memory maps visualization shows wrong offset for register and aligns them wrong.
  • VHDL and Verilog generator will generate wrong values.
  • Port maps will not automatically adjust to changes in port size.
  • VHDL import does not preserve references to model parameters.

Kactus2: Version 2.6.0 released

Added by Esko Pekkarinen about 3 years ago

New features:
+ New plugin interface for file import.
+ New plugins:
  • Verilog import.
  • Verilog generator for components and designs.
  • Makefile generator.

+ Added feature to run import from component editor.
+ Added editing of views to component wizard.
+ Added feature to sort port list by port number.

*Moved VHDL import tool to import plugin.
*Updated MCAPI to version 2.015.
*Updated MCAPI generator.

Kactus2: Version 2.5.0 released

Added by Esko Pekkarinen over 3 years ago

New features:
+ All vendor extensions are conserved in IP-XACT documents.
+ Added feature to insert notes in designs.
+ Added feature to run files e.g. script files from Filesets.
+ Added feature to define default run executable for file types.
+ Improved lock operation: Enables browsing of tabs while the document is locked.
+ Added design column for memories.
+ Improved opening of hierarchical components in design.
+ Added feature to reorder bus interfaces in component editor.

- Fixed library crashing with Abstractor objects.
- Fixed other minor bugs and usability issues.

    (1-10/10)

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