Version 3.9.0 released

Python integration
Added by Esko Pekkarinen about 1 year ago

New PythonAPI for accessing Kactus2 data
+ New interfaces for IP-XACT data read and modify
+ Generator runs for selected generators e.g. Verilog

New Python console in graphical user interface
+ Run interactive scripts
+ View command history
+ Save and run script files

Kactus2 editors adapted to new interfaces
+ Ports
+ Parameters
+ Fields
+ Field resets
+ Registers
+ Address block
+ Memory maps
+ Files
+ File sets
+ Component instantiations
+ Port maps
+ Port abstractions
+ Bus interfaces

Added option to extend port abstractions

Added depenency analysis for (System) Verilog module instantiations

New plugin for CMSIS System View Description (SVD) generation * SVD files can be created from a HW design

Fixed features:
- Fixed crashing when re-importing a file to a Component
- Fixed parameter string value parsing in Verilog import
- Fixed right port boundary in ConnectionEditor
- Fixed port map tables with non-existing ports
- Fixed document writing pointer sharing
- Fixed memory visualization:
  • Changed fields and field gaps for faster updates
  • Fixed label resizing, positioning and clipping
  • Fixed visualization on expanding items
  • Fixed updating register files
  • Updated visualization to correctly display over 32-bit long address ranges