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Version 3.10.0 released

Added by Esko Pekkarinen about 2 months ago

PythonAPI improvements:
+ Bus interfaces and port maps are now accessible through the API

Python console changed to proper text editor in graphical user interface
+ More convenient editing and running of script files

GUI improvements:
+ Port map tree view changed back to table format for better readability and performance
+ Editor title font size increased for bettter navigation
+ Library and component editor trees now automatically expand children until branch is found making navigation easier
+ Kactus2 extensions are now clearly marked in the component editor

Verilog generator improvements:
+ Fixed parameters not being ordered by their dependencies in the module declaration
+ Fixed module parameter referencing component parameters to evaluate correctly, not as the name of the parameter

VHDL import improvement:
+ Fixed VHDL generic import to not stop on a semicolon in comments

CMSIS System View Description (SVD) generator improvement:
+ Register dimension are now written in the generated file

Fixed features:
- Fixed crashing when creating a connection in design with draft bus interfaces
- Fixed crashing when reading invalid XML file
- Fixed crashing for incorrect indexing with memory remaps
- Fixed design schematic reordering bus interfaces in the enclosing component

Changed features:
- File modification outside Kactus2 is no longer detected in the GUI

Structural changes
- Common functions and library handling reloacted to new shared library, KactusAPI


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