Version 2.7.0 released
Version 2.7.0 was released on 6th Februray 2015. New features introduce support for SystemVerilog expressions in component configuration and referencing to parameters/model parameters.
+ Added support for SystemVerilog expressions in * component parameter and model parameter value, * component port bounds and default value, * component register offset, size and dimension and * design configurable element values.
+ Added support for referencing parameter and model parameter values in expressions.
+ Added autocomplete feature for available parameter names in expressions.
+ Added feature to view all elements referencing a parameter or model parameter.
+ Configurable element values editor now automatically shows the configurable elements in component instance, their current and default value.
+ Added feature to show/hide elements of a component in component editor.
+ Added support for component choices.
+ Enabled different signal widths for master and slave modes in abstraction definition.
+ Improved ribbon toolbar.
SystemVerilog expressions are not supported by some features including generators. If expressions or references have been used, it may cause at least the following issues:
- Memory map header generator will generate wrong offsets for registers.
- Memory maps visualization shows wrong offset for register and aligns them wrong.
- VHDL and Verilog generator will generate wrong values.
- Port maps will not automatically adjust to changes in port size.
- VHDL import does not preserve references to model parameters.