Version 3.2.0 released

Added by Esko Pekkarinen almost 2 years ago

+ Added preliminary version of memory designer:
  • Address spaces and Memory maps within design hierarchy are visualized with their addressing information
  • Connectivity between spaces and maps are visualized
+ Added preliminary version of memory connectivity analysis within designs
  • Added plugin for generating memory listing in CSV format

+ Improvements to Verilog generation
+ Added "Getting started" section to help
+ Fixed performance issues

- Fixed crashing when opening a bus interface without abstraction definition

  • ModelSim Generator moved from core to a separate plugin
  • UI issue: paste command does not update usage count of referenced parameters.


Added by Scott wold 26 days ago

An alternate approach is to utilize the major and minor numbers, alongside an alphanumeric string signifying the discharge compose, e.g. "alpha", "beta" or "discharge applicant". A product discharge prepare utilizing this approach may look like 0.5, 0.6, 0.7, 0.8, 0.9 1.0b1, 1.0b2 (with some fixes), 1.0b3 (with more fixes) 1.0rc1 (which, on the off chance that it is sufficiently steady) == 1.0. On the off chance that 1.0rc1 ends up having bugs which must be settled, it transforms into 1.0rc2, et cetera. It is a typical practice in this plan to bolt out new highlights and breaking changes amid the discharge hopeful stages and for a few groups . read more