Version 3.10.0 released

Added by Esko Pekkarinen over 1 year ago

PythonAPI improvements:
+ Bus interfaces and port maps are now accessible through the API

Python console changed to proper text editor in graphical user interface
+ More convenient editing and running of script files

GUI improvements:
+ Port map tree view changed back to table format for better readability and performance
+ Editor title font size increased for bettter navigation
+ Library and component editor trees now automatically expand children until branch is found making navigation easier
+ Kactus2 extensions are now clearly marked in the component editor

Verilog generator improvements:
+ Fixed parameters not being ordered by their dependencies in the module declaration
+ Fixed module parameter referencing component parameters to evaluate correctly, not as the name of the parameter

VHDL import improvement:
+ Fixed VHDL generic import to not stop on a semicolon in comments

CMSIS System View Description (SVD) generator improvement:
+ Register dimension are now written in the generated file

Fixed features:
- Fixed crashing when creating a connection in design with draft bus interfaces
- Fixed crashing when reading invalid XML file
- Fixed crashing for incorrect indexing with memory remaps
- Fixed design schematic reordering bus interfaces in the enclosing component

Changed features:
- File modification outside Kactus2 is no longer detected in the GUI

Structural changes
- Common functions and library handling reloacted to new shared library, KactusAPI

Version 3.9.0 released

Added by Esko Pekkarinen over 2 years ago

New PythonAPI for accessing Kactus2 data
+ New interfaces for IP-XACT data read and modify
+ Generator runs for selected generators e.g. Verilog

New Python console in graphical user interface
+ Run interactive scripts
+ View command history
+ Save and run script files

Kactus2 editors adapted to new interfaces
+ Ports
+ Parameters
+ Fields
+ Field resets
+ Registers
+ Address block
+ Memory maps
+ Files
+ File sets
+ Component instantiations
+ Port maps
+ Port abstractions
+ Bus interfaces

Added option to extend port abstractions

Added depenency analysis for (System) Verilog module instantiations

New plugin for CMSIS System View Description (SVD) generation * SVD files can be created from a HW design

Fixed features:
- Fixed crashing when re-importing a file to a Component
- Fixed parameter string value parsing in Verilog import
- Fixed right port boundary in ConnectionEditor
- Fixed port map tables with non-existing ports
- Fixed document writing pointer sharing
- Fixed memory visualization:
  • Changed fields and field gaps for faster updates
  • Fixed label resizing, positioning and clipping
  • Fixed visualization on expanding items
  • Fixed updating register files
  • Updated visualization to correctly display over 32-bit long address ranges

Version 3.6.0 released

Added by Esko Pekkarinen over 5 years ago

+ Added support to run Kactus2 from command-line without GUI
+ Added editor for port type definitions
+ Added support for multiple abstraction definitions in a bus interface
+ Improvements to Memory Designer
  • Improved item scaling in non-compressed mode
  • Improved search through hierarchies
  • Improved visulization for multiple address spaces connected to one memory map
+ Added feature to save HW, System and Memory Designer view as a PNG, JPG or SVG image
+ Improved expression parsing
  • Support for exp, pow and sqrt functions
  • Better suppport for string expressions and their comparison
  • Faster parsing algorithm

+ Added Linux Device Tree Generator plugin
+ IP-XACT library handling improved for better performance and readability
+ HW and System design area size now adjusts to contents

- Restored automatic item selection in library view when component instance is selected
- Fixed addressSpaceRef-attribute parsing and writing
- Fixed export dialog from hierarchy view
- Fixed missing type information in VHDL generation
- Fixed error in entity parsing in VHDL import
- Fixed a crash when creating a new HW Design
- Fixed a crash in saving user settings for code editor
- Fixed an issue where Component file set directories were lost on refresh

  • Changed binary name to kactus2 (previously Kactus2) in Linux
  • Enabled C++11 by default in Linux compilation
  • Improved Linux installation in user-specified directory
  • Migrated to Qt 5.10.1
  • Migrated to VS2017

Version 3.5.0 released

Added by Esko Pekkarinen almost 6 years ago

+ Graphical user interface visual update:
  • All icons updated
  • Instruction labels added in dialogs
  • Colors centralized in KactusColors.h
+ Added feature to show the directory icons provided by OS for library paths which shows version controlled items in Windows
+ Added feature to automatically update library view when file changes on disk
+ Added feature to select the which HW design to open for an IP-XACT component with multiple designs
+ Added editor for indirect interfaces in component + Added editor for component instantiation parameters
+ Added editor for design configuration instantiation parameters
+ Added editor for design configuration instantiation configurable elements
+ Added editor for design instantiation configurable elements
+ Added feature to define prefix in port map auto-connect for better matching
+ Added editor for design parameters
+ Improved performance on drawing connections in design
+ Added delete in context menu in design view
+ Improvements in Memory Designer:
  • Added support for multiple items accessing the same memory map
  • Improved layout for items + Improvements in HTML generation:
  • Added writing register and field reset values in HTML
  • Added writing instantiations within a component in HTML

- Fixed error in XML schema location writing
- Fixed C source editor refresh
- Fixed port size parsign in PADS part generator which previously caused the plugin to crash
- TLMW generator plugin removed from build

  • Software component instance merged to component instance
  • Changed VHDL import to create component parameters and retains references in port boundaries
  • Moved VHDL generator from core to a separate plugin
  • ModelSim generator plugin moved to same framework as Verilog generator

Version 3.4.0 released

Added by Esko Pekkarinen over 6 years ago

+ Enhanced features for Memory Designer:
  • Added feature to visualize overlapping memory items
  • Added feature to open the containing component and the editor for the selected item
  • Added feature to visualize local memory maps
  • Changed the visual look of a connection through a bridge
  • Changed display name to be shown instead of element name, if defined
+ Improvements to Verilog generation:
  • Added preview for generated files
  • Added message console for reporting generation status
  • Improved port assignment and vector boundary generation logic

+ Fixed error in importing Verilog ports
+ Added editor for Catalogs
+ Component editor layout updated for most editors
+ Enabled expressions in parameter value when using a choice
+ Added isPresent-property to memory maps, address blocks, address spaces and segments
+ Improved completion help for fileset filetypes and groups
+ Enabled CSV import/export of files in a fileset
+ Added feature to hide immediate values from configurable element values
+ Enabled keyboard navigation in VLNV tree view
+ Added expand/collapse options in VLNV tree view context menu
+ Help and tooltips updated
+ Custom XML namespaces are retained in XML files

- Removed address space reference and base address from mirrored-master bus interface
- Fixed crashing when adding port maps in component
- Fixed a referencing issue with configurable element values when changing active view
- Fixed crashing when a design did not have a configuration
- Fixed crashing when closing a design in specific cases
- Fixed modifications to design connections while the document was unlocked
- Fixed CSV import/export of signal definitions in abstraction definition
- Fixed missing component editor visibility options

  • System mode bus interface coloring changed from red to purple to avoid confusion with invalid interfaces
  • Changed "frozen column" in editors to use vertical headers instead of a separate table
  • Toolbar "Check intergrity" changed to show listing of all errors within the library
    in separate window.
  • Exit screen is displayed longer

Version 3.3.0 released

Added by Esko Pekkarinen almost 7 years ago

+ Enhanced features for Memory Designer:
  • Register fields added
  • Compression of items to minimize the required space
    *Multiple address spaces can now be shown as part of the same connection
  • Filtering options added
+ Memory connectivity analysis now manages also instances with identical names
+ File paths within filesets now accept URI expressions
+ Files can be drag-dropped to filesets from the file system
+ Memory map visualization items have now bigger area for expand/collapse
+ Port direction is now checked when a default value is set
+ Port map invert and tieoff are now also shown on the top level of tree hierarchy
+ Zooming now follows mouse location in design
+ Enhanced usage of drafts in design:
  • Bus interface definitions copying when connecting hierarchical draft interface fixed
  • Bus interface definitions copying when connecting non-hierarchical draft interface removed
  • Bus interface definitions and port copying to draft instances changed to take place on packaging of the containing draft component instance
  • Copy-paste of bus interface to a draft component instance changed to copy only the name and the mode of the interface
+ Notification on trying to read XML files of previous standard versions added
+ Improvements to Verilog generation:
  • Generation setup dialog simplified
  • Register definition creation set as optional
  • Module name is correctly used for component instances
  • Environmental identifier created by the generator changed
+ Improvements to Verilog import:
  • Port type parsing improved for Verilog-2001 style ports
  • Parameter parsing improved for lists of parameters
  • Environmental identifier created by the import changed
+ Improved features for MakefileGenerator:
  • Conflicting file selection added
  • Launcher script creation set to optional

- Bus interface creation wizard fixed from preventing user to proceed from the general settings page due to missing port maps
- Component instance replace in design changed to better preserve existing connections
- Port bounds for ad-hoc connections in design fixed
- Author information read from XML fixed
- Symbolic file link usage for XML files fixed
- Toolbar placement at the bottom of main window fixed
- Software views are replaced by views and component instantiations

  • Community guidelines included in manual
  • Settings file path is now shown on the General page of Settings
  • Automatic port mapping changed to less aggressively connect ports
  • Component instance architecture changed to be correctly set by VHDL generator

Version 3.2.0 released

Added by Esko Pekkarinen about 7 years ago

+ Added preliminary version of memory designer:
  • Address spaces and Memory maps within design hierarchy are visualized with their addressing information
  • Connectivity between spaces and maps are visualized
+ Added preliminary version of memory connectivity analysis within designs
  • Added plugin for generating memory listing in CSV format

+ Improvements to Verilog generation
+ Added "Getting started" section to help
+ Fixed performance issues

- Fixed crashing when opening a bus interface without abstraction definition

  • ModelSim Generator moved from core to a separate plugin
  • UI issue: paste command does not update usage count of referenced parameters.

Version 3.1.0 released

Added by Esko Pekkarinen over 7 years ago

+ New design for port map editor: * Added feature to auto-connect logical and physical ports * Logical and physical bounds are now easily editable
+ Added support for tieoff values in design and port maps
+ Added feature to copy memory-elements along with their sub-elements
+ Improved expression support: * Basic comparison operators are now accepted * Values true/false are now accepted
+ System group names are now visible and editable in Bus editor
+ Generated Verilog parameters are now correctly ordered for references
+ Performance improvements

  • ModelSim Generator moved from core to a separate plugin
  • XML processing instructions are now retained in IP-XACT files
  • Added option for Linux installation without admin privilidges
  • UI issue: paste command does not update usage count of referenced parameters.

Version 3.0.0 released

Added by Esko Pekkarinen over 7 years ago

+ Updated all IP-XACT elements to 2014 standard
+ Improved validation for many IP-XACT elements
+ Updated Verilog generation for one-to-many ad-hoc connections.
+ Added new view related editors for component editor: * Component instantiations * Design instantiations * Design configuration instantiations.
+ Updated port editor to accept ports without defined left and right bounds as ports with a width of 1.
+ Updated parameter referencing.
+ Updated expression parser.
+ Updated component editor memory map visualization.
+ In component editor, changed cut command to copy and remove selected cells of a table.
+ Updated HW design editor: * Updated component instance creation. * Updated component instance removing. * Updated component instance replacing. * Updated connection removing. * Invalid ad-hoc interfaces and ports are displayed with a red colour. * Enabled deleting of invalid ad-hoc interfaces and ports.
+ Usability fixing.

  • UI issue: paste command does not update usage count of referenced parameters.

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