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Version 2.8.0 released

Added by Esko Pekkarinen over 7 years ago

+ Added feature to import parameters from include files.
+ Improved configurable element variables editor
  • Synchronizes with the enhanced model parameter definition.
  • The parameters of the top component can be used in the configurable element variables.
  • Variables are now grouped according to their location in the component.

+ Added editors for IP-XACT elements remapState and memoryRemap.
+ Added support for expressions in memory map elements.
+ Added support for parameter references in generated header files.
+ Added feature to save new versions of design configurations and designs.
+ Added support for module parameters to hierarchical views.

KNOWN UNRESOLVED ISSUES:
  • Memory map header generation from a system design does not work properly.
  • Parameters created with version 2.7.0 may not work with the latest release due to change in id formatting. The fastest way to fix this is to re-create the parameters.
  • SystemVerilog expressions are not supported by some features including generators. If expressions or references have been used, it may cause at least the following issues:
    • VHDL generator will generate wrong values.
    • Port maps will not automatically adjust to changes in port size.
  • VHDL import does not preserve references to model parameters.
  • In ports editor, creating a bus interface through ports is not possible for name column.

Version 2.7.0 released

Added by Esko Pekkarinen over 7 years ago

New features:
+ Added support for SystemVerilog expressions in * component parameter and model parameter value, * component port bounds and default value, * component register offset, size and dimension and * design configurable element values.
+ Added support for referencing parameter and model parameter values in expressions.
+ Added autocomplete feature for available parameter names in expressions.
+ Added feature to view all elements referencing a parameter or model parameter.
+ Configurable element values editor now automatically shows the configurable elements in component instance, their current and default value.
+ Added feature to show/hide elements of a component in component editor.
+ Added support for component choices.
+ Enabled different signal widths for master and slave modes in abstraction definition.
+ Improved ribbon toolbar.

KNOWN UNRESOLVED ISSUES:
SystemVerilog expressions are not supported by some features including generators. If expressions or references have been used, it may cause at least the following issues:
  • Memory map header generator will generate wrong offsets for registers.
  • Memory maps visualization shows wrong offset for register and aligns them wrong.
  • VHDL and Verilog generator will generate wrong values.
  • Port maps will not automatically adjust to changes in port size.
  • VHDL import does not preserve references to model parameters.

Version 2.6.0 released

Added by Esko Pekkarinen almost 8 years ago

New features:
+ New plugin interface for file import.
+ New plugins:
  • Verilog import.
  • Verilog generator for components and designs.
  • Makefile generator.

+ Added feature to run import from component editor.
+ Added editing of views to component wizard.
+ Added feature to sort port list by port number.

*Moved VHDL import tool to import plugin.
*Updated MCAPI to version 2.015.
*Updated MCAPI generator.

Version 2.5.0 released

Added by Esko Pekkarinen about 8 years ago

New features:
+ All vendor extensions are conserved in IP-XACT documents.
+ Added feature to insert notes in designs.
+ Added feature to run files e.g. script files from Filesets.
+ Added feature to define default run executable for file types.
+ Improved lock operation: Enables browsing of tabs while the document is locked.
+ Added design column for memories.
+ Improved opening of hierarchical components in design.
+ Added feature to reorder bus interfaces in component editor.

- Fixed library crashing with Abstractor objects.
- Fixed other minor bugs and usability issues.

(11-14/14)

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