Esko Pekkarinen

  • Registered on: 01.08.2013
  • Last connection: 19.04.2017

Projects

  • Kactus2 (Manager, Developer, 01.08.2013)

Activity

Reported issues: 126

30.03.2017

12:09 pm Kactus2 Feature #345 (New): RTL Register map generation
Add feature to generate register map in RTL.
*Implementation details:*
*...

23.03.2017

02:25 pm Kactus2 Bug #342 (In Progress): Missing default value for unused bits
DefaultValue_432_3: I agree the default values for data1 and en1 should come from the port definition and not from th...

22.03.2017

02:50 pm Kactus2 Version 3.4.0 released
+ Enhanced features for Memory Designer:
* Added feature to visualize overlapping memory items
* Added feature ...

10.03.2017

10:07 am Kactus2 Bug #341 (Closed): Verilog import detects wrong port direction
07:43 am Kactus2 Bug #341 (In Progress): Verilog import detects wrong port direction

06.03.2017

07:59 am Kactus2 Bug #335 (In Progress): Subvector assignment incomplete

23.02.2017

01:06 pm Kactus2 Bug #335 (Resolved): Subvector assignment incomplete
Already fixed.

22.02.2017

08:52 am Kactus2 Feature #333 (Closed): Missing port type wire

16.02.2017

08:35 am Kactus2 Feature #330 (Closed): Keyword highlight for generation preview

07.02.2017

10:21 am Kactus2 Feature #296 (Closed): Add IP-XACT catalog element

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